Introduction and Principle of Operation of the DSC


Digitization of fast detector signals has become essential in many different detector systems. It enables a detailed evaluation of piled-up pulses from scintillators as well as improved time resolution of gas detector pulses. The Domino Sampling Chip (DSC) is an analog CMOS waveform sampling device, designed at PSI and dedicated to the PIBETA detector. In future, it can be used as a cheap device in experiments with high multiplicity of readout channels. This article describes the test results of the prototype DSC.

Principle of Operation

The 128-bin DSC is realized in a 1.2 micron-process (SACMOS1), i.e. the minimal width of conducting lines and diffusion. areas of field effect transistors (FET's) is 1.2 micron; the chip is fabricated by FASELEC AG.

The operation of the DSC consists of the sampling phase and the readout phase. The principle of the sampling mechanism can be explained by a domino wave model: A logic pulse is transmitted through two sequential CMOS inverters and therefore reproduced; since the retardation of an inverter is ~500ps, the pulse is delayed by ~1ns. Thus a signal propagating through a long chain of inverters acts like a domino wave. The circuit diagram of the DSC is shown in Fig.1 :

Fig.1: Circuit Diagram of the DSC.

A positive edge applied at the SDW (start domino wave) pad starts the domino wave which after every second inverter connects the read-in line with a storage capacitor; therefore the instantaneous level of the read-in line voltage is hold. The width of the domino wave is controlled by the domino wavelength voltage. The domino speed voltage V_DS influences the propagation time of the domino wave and therefore the sampling speed. In the present version, this mechanism works from ~0.4...~1.2 GHz, as shown in Fig. 2.

Fig.2: Sampling speed vs V_DS.

The input signal is DC coupled to the INPUT S pad. The read out of the stored information is done by applying four signals (see Fig.1): The RBI (read bit in) pulse, which is clocked through the read-out shift register with the signals Phi1, Phi2. A usual cyclus for the DSC is described here.

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Ch. Broennimann, 6. Jan 1995
last update: H.P. Wirtz, 09-Aug-2000