DSC Test Environment


Digitization of fast detector signals has become essential in many different detector systems. It enables a detailed evaluation of piled-up pulses from scintillators as well as improved time resolution of gas detector pulses. The Domino Sampling Chip (DSC) is an analog CMOS waveform sampling device, designed at PSI and dedicated to the PIBETA detector. In future, it can be used as a cheap device in experiments with high number of readout channels.

500 DSC are available for the PIBETA experiment now. Before building DSC modules we have to test the chips individually. Testing means, that we have to check, if the Readbit will be clocked through the shift register and if the sampling works recently. We operate a single DSC in a 'simple mode' and look if the Readbit will be clocked through the readout shift register and the signal output shows that a pulse on the input is sampled.

We've measured the response of the Zero Suppression. We measure the threshold voltage, when the Zero Suppression starts working  for a DC offsetted pulse. Variation of  the Domino Speed voltage should show a different output for a fixed signal. If these criteria are fulfilled, the chip is accepted and ready for motherboard production.

Test Setup

To test all 500 chips individually, it is necessary to make electrical contacts very flexible. The electrical coupling is established by a probe card, specially designed for the DSC by  Wentworth Laboratories GmbH. For fast exchange of the chips and easy contacting between probe card and chip we use use a special mechanical structure. The digital control signals are produced by a CAMAC module CPG 501 sequencer.

Mechanical Structure

DSC Test Setup Figure 1: DSC Test Setup

The chips are on blocks of 6 each. This blocks are held by vacuum to keep them in a fixed position, without the use of glue. We have a cube of  Plexiglas (figure 2) with 3 drains and a connection to a vacuum pump.

plexi cube Figure 2: Plexiglas Cube

This block is mounted on a x-y-table to adjust the x-y position of the chip relative to the probecard needles. The probecard is fixed on an independent table, moveable in z-direction. When the chip is in its right position one can move the card downward to contact the needles to the bondpads of the chips. A stereo microscope is used to control the right positioning.

Power Supply And Logical Signals

The chip needs (minimal) 5 digital steering signals and a few DC voltages for operation. All signals and voltage levels are coupled to the chip via the probecard.

DSC Probecard Figure 3: Probecard connections to power supply and sequencer

A full table of connections, used by the DSC in the test setup is given here in table 1:
Probe Pin Pad # Signal Comment
2 11 V- dig 1.3V-, Test 0V
5 13 Gate CPG
6 15 RBI CPG
7 17 Clear=Reset CPG
12 18 Threshold voltage divider, variable
14 2 GND ana 0V, Test +1.2V 1/3 V+
18 4 RBO RBO Pin
19 6 Phi 1 CPG
24 9 V + 3.7 V +
A 10 V - dig 1.3V-, Test 0V
AA 8 V + 3.7 V +
D 12 V ds voltage divider, variable
E 14 En ZS voltage divider, switched
F 16 3-pad internal jumpered
N 19 Input pulse generator
P 1 V add last 4 cells not in Test
U 3 Output Output Pin
V 5 ROR internal jumpered
W 7 Phi 2 CPG
Table 1: DSC Connections via probecard


Logical Signals

The digital steering signals are produced by a 12 bit sequencer CPG 501, externally clocked by 1 MHz. A simple sequence is shown in figure 3. The DSC requires TTL levels, but the CPG module gives just +2.6 V (logical 1) on 50 Ohms out. But it is possible to operate the DSC with this minor voltage by reducing the DC voltage V+ from 4.5 V to 3.7 V.

Figure 3: Example for a simple Control Sequence for the DSC

DC Voltages

The DC voltages are provided by a voltage divider unit, connected to an external source (lab power supply). The voltage divider is selfmade (see figure 4).

Figure 4: DSC Voltage Divider Circuit Diagram


Output Driver

The output of the DSC analog output has not enough power for the connection to the FADC (in our test setup it is the SIROCCO III). So we have to 'blow up' the output signals. We are using the HA5022 OpAmp for this purpose. The circuit diagram and the pin connection are shown in figures 5 and 6.

Output Driver
Figure 5: DSC Output Driver Circuit Diagram

Pin Connection HA 5022 Operation Amplifier
Figure 6: HA 5022 OpAmp pin connections. V+, V- = +/-5 V (symmetrically!!!)

Results on the DSC Test
DSC Test Database

Return to the DSC Main Page


H.P. Wirtz, Dec-1998
last update 09-Aug-2000