Nanoscale Structural/ Stress Chemical Measurements in Microelectronic Devices (MARCO)



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contact persons: Dalavar Anjum (dha6n@virginia.edu); Jian Li (jl2md@virginia.edu)


The current Si-based CMOS technology will end at 35 nm according to ITRS 1999. New materials, structures, and devices beyond those envisioned in the ITRS will be required in the future to meet the needs of semiconductor industry. The whole mission of Microelectronics Advanced Research Corp. (MARCO) Focus Center for Materials Structure and Device (FC-MSD) are to determine and explore the most promising path for microelectronics in the next 20~30 years. This project is supported by Semiconductor Industry Association (SIA) and DARPA and overall led by MIT. Tasks of this project include: Sub-10-nm Silicon-Based FETs; Silicon-Based Quantum Effects Devices; Molecular and Organic-Semiconductor Electronics.

The aim of MARCO at UVA is twofold namely;

1.       To develop new techniques for nanometer-scale strain characterization of the new ultra-thin Strained-Si/Ge devices in collaboration with Prof. Judy Hoyt’s group at MIT.

2.       Ultra high resolution imaging of structure, defects, chemistry and crystallography of device structures.

Strained-Si/Ge devices are very promising because of the high electron and hole mobility and compatibility with standard Si-based CMOS processing. With the decrease of the dimension of the devices, the nanoscale strain characterization technique in the strained Si/Ge device becomes extremely necessary and difficult. The traditional strain measurement techniques such as X-ray micro-diffraction and Micro-Raman can only have a spatial resolution of about 0.5 to 1 mm. We develop a new technique to measure the stresses with a spatial resolution on the order of nm and relative sensitivity on the order of tens of MPa. This new technique involves the utilization of TEM and FIB characterization techniques in conjunction with an ensemble of computer programs that include finite element modeling (FEM), electron diffraction contrast (EDC) simulations, and image manipulations.

Fig.1 shows an example of nano-scale stress analysis with FEM and EDC simulations.









Fig .1 (400) BF micrograph of SiGe HBT device and its FEM stress plot in SiGe.

Here in Figs. 2-6, we apply this technique to another type of devices i.e. Strained-Si MOSFETs to show the complete procedure of stress characterization. Based upon the successful quantification of stresses in both HBTs and MOSFETs devices, we infer that this technique may be applied to all kinds of devices with the dimensions as small as 10nm. The detailed methodology is as follows:

  • We first use the focus ion beam (FIB) to make an uniform thickness cross-section sample and take the bright field TEM image, as shown in Fig. 2.

  •  Busing known specimen geometry and measured intrinsic stresses and applying the wafer curvature method, an accurate computer model of stresses within structure can be achieved using FEM, as shown in  Fig.3.





Text Box: Fig.2  (400) BF image of SiGe MOSFET, Gate length is 100nm


Text Box: Fig.3 FEM of the stress distribution


  • The FEM data can be exported into a program called SIMCON, which mathematically solves the dynamical electron diffraction equations, to give the simulated EDC image as shown in Fig.4.




Text Box: Fig. 4 Simulated TEM image



Text Box: Fig.5 Difference map with scale bar representing the GL difference.


  • The simulated and experimental images are matched by creating difference map of gray scale as shown in Fig 5.

  • SIMCON simulations are then performed for series of load conditions

  • Finally, these are matched with the experimental TEM image to find the best load conditions which give rise to the final stress quantification.

Figures 6a and 6b show the defect analysis of Strained-Si/Ge devices (50 mm long-channel MOSFETs) using TEM. The defect complexes are created by Si+ ion-implantation in strained-Si channel region and subsequently the samples are RTA annealed at 1000 °C for one second (Fig. 7a) and ten seconds (Fig. 6b). The TEM specimens of Strained-Si/Ge devices are prepared using FIB and are analyzed with 200 keV TEM under {400} dynamical 2-beam conditions. The defect complexes are not removed much after the one second RTA annealing. It is determined that some of the defects are vacancy loops exhibiting “Coffee-Beans Contrast” visible in Fig. 6a. However, most the defects are removed after annealing for ten seconds. The removal of the defects via annealing causes stresses in the underlying Si-Ge layers which can be seen in the Fig. 6b.